? semiconductor components industries, llc, 2010 december, 2010 ? rev. 2 1 publication order number: nb3n3020/d nb3n3020 3.3 v, lvpecl/lvcmos clock multiplier description the nb3n3020 is a high precision, low phase noise selectable clock multiplier. the device takes a 5 ? 27 mhz fundamental mode parallel resonant crystal or a 2 ? 210 mhz l vcmos single ended clock source and generates a differential lvpecl output and a single ended lvcmos/lvttl output at a selectable clock output frequency which is a multiple of the input clock frequency. three tri ? level (low, mid, high) lvcmos/lvttl single ended select pins set one of 26 possible clock multipliers. an lvcmos/lvttl output enable (oe) tri ? states clock outputs when low. this device is housed in 5 mm x 4.4 mm narrow body tssop 16 pin package. features ? selectable clock multiplier ? external loop filter is not required ? lvpecl differential output ? lvcmos/ lvttl outputs ? rms period jitter of 5 ps ? jitter or low phase noise at 125 mhz [25 mhz input]: offset noise power 100 hz -95 dbc/hz 1 khz -107 dbc/hz 10 khz -112 dbc/hz 100 khz -117 dbc/hz 1 mhz -117 dbc/hz 10 mhz -134 dbc/hz ? operating range 3.3 v 10% ? industrial t emperature range ? 40 c to +85 c ? these are pb ? free devices marking diagram tssop ? 16 dt suffix case 948f http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information 1 16 a = assembly location l = wafer lot y = year w = work week = pb ? free package nb3n 3020 alyw 1 16 (note: microdot may be in either location) (top view) pin configuration oe2 vdd clk2 clk2 gnd vdd clk1 gnd vdd x1/clk x2 sel2 sel1 sel0 oe1 gnd 116
nb3n3020 http://onsemi.com 2 phase detector loop filter vco clock buffer/ crystal oscillator %n select control block pre sca ler lv ? cmos/ lv ? pecl output vdd gnd oe2 oe1 clk1 clk2 sel0 sel1 sel2 x2 x1 / clk 5 ? 27 mhz crystal or 2 ? 210 mhz clock figure 1. nb3n3020 simplified logic diagram lv ? ttl output clk2 table 1. pin description pin name i/o description 6 sel0 tri ? level input frequency select input 0. when left open, defaults to vdd/ 2. see output select table 2 for details. 5 sel1 tri ? level input frequency select input 1. when left open, defaults to vdd/ 2. see output select table 2 for details. 4 sel2 tri ? level input frequency select input 2. when left open, defaults to vdd/ 2. see output select table 2 for details. 1, 11, 15 vdd power supply positive supply voltage pins are connected to +3.3 v supply voltage. 2 x1/clk input crystal or clock input. connect to 5 ? 27 mhz crystal source or 2 ? 210 mhz single ? ended clock. see table 2. 3 x2 input crystal input. connect to a 5 ? 27 mhz crystal or leave unconnected for clock input. see table 2. 7, 16 oe1, oe2 input output enable input that tri ? states clock outputs when low. internal pull ? up resistor to vdd. oe1 is designated to control lv cmos output synchronously and oe2 is designated to control lv pecl output synchronously. see operation details in device operation. 8, 9, 12 gnd power supply ground 0 v. these pins provide gnd return path for the devices. 13 clk2 lvpecl output inverted clock output. clock frequency equals input frequency times multiplier. 14 clk2 lvpecl output non ? inverted clock output. clock frequency equals input frequency times multiplier. 10 clk1 lvttl/ lvcmos output clock output. clock frequency equals input frequency times multiplier.
nb3n3020 http://onsemi.com 3 table 2. output frequency clock multiplier select table sel2 sel1 sel0 clk1, clk2, clk2 clock input range [mhz] crystal input range [mhz] l l l low (power down) ? ? l l m input x 1 25 ? 210 25 ? 27 l l h input x 4/3 (or 1 1/3) 15 ? 157.5 15 ? 27 l m l input x 1.5 10 ? 140 10 ? 27 l m m input x 5/3 (or 1 2/3) 25 ? 131.25 25 ? 27 l m h input x 1.875 40 ? 112 ? l h l input x 2 25 ? 105 25 ? 27 l h m input x 7/3 (or 2 1/3) 15 ? 90 15 ? 27 l h h input x 2.4 25 ? 87.5 25 ? 27 m l l input x 2.5 10 ? 84 10 ? 27 m l m input x 8/3 (or 2 2/3) 15 ? 78.75 15 ? 27 m l h input x 3 15 ? 70 15 ? 27 m m l input x 3.125 40 ? 67.20 ? m m m input x 3.2 25 ? 65.63 25 ? 27 m m h input x 10/3 (or 3 1/3) 15 ? 63 15 ? 27 m h l input x 3.75 20 ? 56 20 ? 27 m h m input x 4 2 ? 52.5 5 ? 25 m h h input x 5 6 ? 42 6 ? 27 h l l input x 6 5 ? 35 5 ? 27 h l m input x 6.25 20 ? 33.6 20 ? 27 h l h input x 19/3 (or 6 1/3) 15 ? 33.16 15 ? 27 h m l input x 8 5 ? 26.25 5 ? 26.25 h m m input x 25/3 (or 8 1/3) 15 ? 25.2 15 ? 25.2 h m h input x 10 5 ? 21 5 ? 21 h h l input x 12 5 ? 17.5 5 ? 17.5 h h m input x 12.5 10 ? 16.8 10 ? 16.8 h h h input x 16 5 ? 13.125 5 ? 13.125 l ? low, m ? mid, h ? high recommended crystal parameters crystal fundamental at ? cut frequency 5 ? 27 mhz load capacitance 16 ? 20 pf shunt capacitance, c0 7 pf max equivalent series resistance 35 max initial accuracy at 25 c 20 ppm temperature stability 30 ppm aging 20 ppm c0/c1 ration 250 max device operation the nb3n3020 is a clock multiplier. the device can take crystal or clock input and generates lvpecl and lvcmos/ l vttl clock outputs which are multiples of the input as determined by the tri ? level select inputs [sel0, sel1, sel2]. clock multiplication nb3n3020 is a clock multiplier with the clock multiplier selected by the tri level select inputs [sel0, sel1, sel2]. nb3n3020 has a lvttl/lvcmos output [clk1] and a lvpecl clock output [clk2, clk2 ]. output enable the device has an output enable [oe] which is used to tri ? state the outputs. oe1 controls the clk1 clock output where as oe2 controls the clk2, clk2 clock outputs. when oe1or oe2 are disabled, the respective clock output(s) are tri ? stated. in this mode of operation, pll is still running, with the respective clock outputs tri ? stated. when the oe1 or oe2 are enabled, the clock outputs
nb3n3020 http://onsemi.com 4 become active synchronous to the internal pll output clock and do not create any glitches or runt pulses during the transition. in power down mode, the outputs are tri ? stated regardless of the state of the oe1, oe2. changing clock multiplier the clock output frequency can be dynamically changed using sel0, sel1, sel2 pins. when the clock frequency is changed, the clock outputs move from one frequency to another and the pll locks to the new frequency within a settling time of 3 msec. there is no glitch during this transition when the clock outputs are active {not tri ? stated by oe1, oe2}. crystal/ clock input the device takes in a 5 ? 27 mhz crystal input or 2 ? 210 mhz clock input. once powered up, the input frequency is fixed and should not be changed dynamically. the input cannot accept a spread spectrum clock and needs a fixed frequency clock for device operation. the input frequencies for clock and crystal input for specific multipliers are determined by table 3. power up when the nb3n3020 is powered up, it takes 10 msec for the pll?s to stabilize and lock to the desired frequency of operation as selected by sel0, sel1, sel2. during this time period, there may be glitches in the clock outputs. power down: the device can be powered down when the sel0, sel1, sel2 pins are all connected to gnd. in this mode of operation, pll is turned off and the device consumes less than 5 ma of current. there may be a glitch in clock outputs when the device is powering down. in power down mode, the outputs are tri ? stated regardless of the state of the oe1, oe2. in the cases where the application requires glitch ? less transitions, in order to avoid glitches it is recommended to use synchronous oe signaling to mask glitches to the clock outputs. table 3. attributes characteristics value esd protection human body model 2 kv moisture sensitivity, indefinite time out of dry pack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 8287 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v dd positive power supply gnd = 0 v 4.6 v v i input voltage (vin) gnd = 0 v gnd v i v dd ? 0.5 v to v dd + 0.5 v v i out lv pecl output current continuous surge 25 50 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 16 tssop ? 16 138 108 c/w jc thermal resistance (junction ? to ? case) (note 3) tssop ? 16 33 to 36 c/w t sol wave solder 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
nb3n3020 http://onsemi.com 5 table 5. dc characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) symbol characteristic min typ max unit v dd power supply voltage 2.97 3.3 3.63 v i dd power supply current (note 4) 60 75 ma i ddoe power supply current when oe1, oe2 is set low 50 ma i ddoff power supply current when pll is powered off by sel0, sel1, sel2 5 ma v ih input high voltage (x1/clk, oe1, oe2) 2000 v dd + 300 mv v il input low voltage (x1/clk , oe1, oe2) gnd ? 300 800 mv v ih input high voltage (sel0, sel1, sel2) 0.72 v dd v dd + 300 mv v il input low voltage (sel0, sel1, sel2) gnd ? 300 800 mv v im input mid voltage (sel0, sel1, sel2) (when left open, defaults to v dd /2 v dd /2 mv v oh output high voltage for clk2, clk2 (see figure 3) v dd ? 1.145 v dd ? 0.895 v v ol output low voltage for clk2, clk2 (see figure 3) v dd ? 2.090 v dd ? 1.600 v v oh output high voltage for clk1 [i oh = ? 12 ma] 2.4 v v ol output low voltage for clk1 [i ol = 12 ma] 0.4 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measurement taken at 125 mhz with lv ? pecl & lv ? cmos/ lv ? ttl outputs not terminated. table 6. ac characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) (note 5) symbol characteristic min typ max unit f clkin crystal input frequency 5.0 27 mhz f clkin clock input frequency 2.0 210 mhz f clkout output clock frequency 210 mhz noise phase ? noise performance (f clkout = 125 mhz, 25 mhz input) @ 100 hz offset from carrier ? 95 dbc/hz @ 1 khz offset from carrier ? 107 dbc/hz @ 10 khz offset from carrier ? 11 2 dbc/hz @ 100 khz offset from carrier ? 11 7 dbc/hz @ 1 mhz offset from carrier ? 11 7 dbc/hz @ 10 mhz offset from carrier ? 134 dbc/hz tjitter p ? p cycle to cycle jitter peak to peak (note 6) f clkout = 125 mhz, 25 mhz input 20 36 ps tjitter rms cycle to cycle jitter rms (note 6) f clkout = 125 mhz, 25 mhz input 5.0 9.0 ps tjitter p ? p period jitter peak to peak (note 7) f clkout = 125 mhz, 25 mhz input 15 20 ps tjitter rms period jitter rms (note 7) f clkout = 125 mhz, 25 mhz input 3.0 5.0 ps start up time from power up 10 ms note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. measurement taken with outputs terminated with 50 ohms to v dd ? 2 v. see figure 2. 6. sampled with 1000 cycles 7. sampled with 10000 cycles
nb3n3020 http://onsemi.com 6 table 6. ac characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) (note 5) symbol unit max typ min characteristic oe output enable/disable time 10 us pll settling time 3 ms t duty_cycle output clock duty cycle (measured at cross point for lv pecl clock output and vdd/2 for lvcmos/ lvttl clock output) 45 50 55 % t r output rise time (note 5) (measured from 20% to 80%. figure 2) lv pecl output 340 700 ps t f output fall time (note 5) (measured from 20% to 80%. figure 2) lv pecl output 340 700 ps t r output rise time (measured from 0.8 to 2 v, no load) lvcmos/ lv ttl output 1500 ps t f output fall time (measured from 2.0 v to 0.8 v, no load) lvcmos/ lv ttl output 1500 ps t r / t f input rise time/ fall time for lv cmos/ lv ttl clock input [x1/clk] 0 1500 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. measurement taken with outputs terminated with 50 ohms to v dd ? 2 v. see figure 2. 6. sampled with 1000 cycles 7. sampled with 10000 cycles lv ? pecl driver receiver device clk2 figure 2. typical termination for output driver for device evaluation r l = 50 r l = 50 v dd ? 2 v z = 50 z = 50 clk2b 80% 20% 340 ps figure 3. lv ? pecl output parameter characteristics 80% 20% 340 ps v dd ? 0.9 v v dd ? 1.7 v t r t f
nb3n3020 http://onsemi.com 7 ordering information device package shipping ? nb3n3020dtg tssop ? 16 (pb ? free) 96 units / rail NB3N3020DTR2G tssop ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3n3020 http://onsemi.com 8 package dimensions tssop ? 16 case 948f ? 01 issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
nb3n3020 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb3n3020/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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